1. Field of the Invention
The present invention relates to a nonvolatile memory device in which a hysteresis characteristic of a polarization in ferroelectric substance related to an electric field is utilized.
2. Description of the Prior Art
When a sufficiently strong electric field is applied to ferroelectric substance like PZT (lead(Pb) Zirconate Titanate), a direction of a polarization is aligned to a direction of the electric field. This alignment still remains after the electric field is removed; that is, the polarization caused in the ferroelectric substance exhibits a hysteresis characteristic related to an applied electric field. Thus, a nonvolatile memory device, utilizing such a hysteresis characteristic, may be designed and fabricated.
The nonvolatile memory device using ferroelectric substance is, for example, disclosed in U.S. Pat. No. 4,873,664. In this nonvolatile memory device, each of memory cells arranged in a matrix manner on a semiconductor substrate has a circuit structure as shown in FIG. 12. Each memory cell includes two field effect transistors (FETs) 1 and 2, which have their respective gates connected to a word line WL and their respective drains connected to bit lines BL1 and BL2, respectively. Moreover, the FETs 1 and 2 have their respective sources connected to one of the plates of ferroelectric capacitors 3 and 4, respectively. The other plates of the ferroelectric capacitors 3 and 4 are connected to a line PLATE. A potential of the line PLATE is controlled by circuitry (not shown). In this way, the memory cell is similar in circuit structure to a memory cell of a DRAM (Dynamic Random Access Memory).
The ferroelectric capacitors 3 and 4 store complementary data; that is, when a polarization is caused in ferroelectrics of the ferroelectric capacitor 3 with its part close to the FET 1 assuming a positive polarity, a polarization is caused in ferroelectrics of the ferroelectric capacitor 4 with its part close to the FET 2 assuming a negative polarity. This state corresponds to a state of data "1" in storage, for example. In a state of data "0" in storage, the states of polarization in the ferroelectrics of the ferroelectric capacitors 3 and 4 are reversed.
In reading data, voltage at High level is applied to the line PLATE. Then, voltage is applied to the word line WL to turn the FETs 1 and 2 on, and the potential difference between the bit lines BL1 and BL2 at this time is amplified by a sense amplifier to read data. If, for example, the data "1" is stored in the memory cell, the polarization caused in the ferroelectric capacitor 3 is identical in direction to an electric field applied thereto. Thus, there is almost no change in the state of the ferroelectrics of the ferroelectric capacitor 3. However, the polarization caused in the ferroelectric capacitor 4 is reverse in direction to an electric field applied thereto. Hence, the direction of the polarization is inverted in the ferroelectric capacitor 4. This results in a potential of the bit line BL2 rising while that of the bit line BL1 is almost unchanged. Thus, by detecting the potential difference between the bit lines BL1 and BL2, the reading of stored data is attained.
In the ferroelectric capacitor 4, however, inversion of the polarization is caused, and therefore, a state of the memory cell varies from that before the reading of data; that is, stored data is destroyed.
Then, the sense amplifier applies voltage at High level to either one of the bit lines BL1 and BL2 which is higher in potential, and it applies voltage at Low level to the other. Under the condition, a potential of the line PLATE is inverted from High level into Low level. As a consequence, an electric field in a direction from the FET 2 toward the line PLATE is applied to the ferroelectric capacitor 4. This causes the direction of the polarization in the ferroelectric capacitor 4 to invert to the direction of the electric field, that is, the direction before the reading of data. In this way, self restoration is performed to reproduce stored data.
However, since the circuit structure of the memory cell is similar to that of the DRAM, electric charge accumulated in the ferroelectric capacitors 3 and 4 is reduced because of junction leakage current or transistor leakage current as time elapses, and sooner or later the stored contents are lost. To maintain the stored contents, refreshing must be implemented to reproduce the contents at fixed time intervals. The refreshing permits current to flow to charge/discharge the ferroelectric capacitors 2 and 3, and this causes the problem that a large power demand in standby is unavoidable.
Also, self restoration is required in the memory cell to reproduce data because the reading operation causes stored data to be destroyed, and this is why polarization inversion in ferroelectrics occurs so frequently. Thus, the ferroelectrics do not take long to deteriorate, and the problem arises that it is not reloadable so frequently. Usually more than 10.sup.12 occurrences of polarization inversion causes ferroelectrics to deteriorate, and the memory cell mentioned above which requires polarization inversion even in the reading of data may be reloadable extremely infrequently.
The prior art which solved these problems is disclosed in U.S. Pat. No. 4,809,225. A circuit structure of a memory cell employed in this prior art is shown in FIG. 13. The memory cell includes a volatile portion 101 and a nonvolatile portion 102. The volatile portion 101 has a circuit structure similar to that of a memory cell of an SRAM (Static Random Access Memory). For example, the volatile portion 101 has a flip flop circuit 14 consisting of P channel FETs 10, 11 and N channel FETs 12, 13 to store data. A data writing/reading FET 15 is coupled between the flip fop circuit 14 and a first bit line BL1. Similarly, a data writing/reading FET 16 is coupled between the flip flop circuit 14 and a second bit line BL2. In writing data, complementary data are applied to the bit lines BL1 and BL2. The FETs 15 and 16 have their respective gates connected to a word line WL.
A node N1 between the flip flop circuit 14 and the writing/reading FET 15 is connected in series with a FET 19a and a ferroelectric capacitor 17 contained in the nonvolatile portion 102. Similarly, a node N2 between the flip flop circuit 14 and the writing/reading FET 16 is connected in series with a FET 19b and a ferroelectric capacitor 18 contained in the nonvolatile portion 102. Nodes N3 and N4 between the ferroelectric capacitors 17, 18 and the FETs 19a, 19b are connected to shorting transistors 19c, 19d, respectively.
In an ordinary operation, a logic signal CLK3 causes the transistors 19a and 19b to turn off, and the logic signal CLK1 is kept at High level. This allows the nonvolatile portion 102 to be electrically disconnected from the volatile portion 101, the whole memory device including this memory cell functions as an SRAM.
Just before power goes OFF, a logic signal CLK4 is kept at Low level to turn the transistors 19c and 19d off while the logic signal CLK3 is kept at High level to turn the transistors 19a and 19b on. This permits the ferroelectric capacitors 17 and 18 to be charged. Under this condition, a logic signal CLK2 is kept at Low level for a certain period of time and then kept at High level for the succeeding period of time. If the node N1 is at High level while the node N2 is at Low level, a polarization is caused in ferroelectrics of the ferroelectric capacitor 17 with its part close to the node 1 assuming a positive polarity, and a polarization is caused in ferroelectrics of the ferroelectric capacitor 18 with its part closed to the node 2 assuming a negative polarity. These polarizations are retained after power goes OFF. Thus, maintenance of data can be effected during a power interruption by transferring data in the volatile portion 101 to the nonvolatile portion 102.
When power is ON, the logic signals CLK 3 and CLK4 are kept at High level to precharge the nodes N1 and N2 with 0 volt, and thereafter, the logic signal CLK 4 turns to Low level. This allows voltage developed in the ferroelectric capacitors 17 and 18 to be applied to the nodes N1 and N2, respectively. In this way, data accumulated in the nonvolatile portion 102 is transferred to the volatile portion 101.
In this prior art technology, the circuit structure of the memory cell is similar to that of a memory cell of an SRAM, and therefore, no refreshing is needed. This leads to less power demand in standby. The polarization caused in ferroelectrics of the ferroelectric capacitors 17 and 18 is not inverted for a period while power is ON and an ordinary operation is carried out. Hence, the number of times the memory cell is reloadable is not decreased.
However, the memory cell in FIG. 13 includes six transistors in the volatile portion 101 and four transistors and two capacitors in the nonvolatile portion 102. Thus, compared with an ordinary SRAM, an extra four transistors and two capacitors are required per cell. This leads to a requirement of an increased cell area, and accordingly the resultant memory cell costs much more. In addition to that, a control circuit for controlling connection/disconnection between the volatile portion 101 and the nonvolatile portion 102 is required, and the problem arises that its structure is complicated